Home Content manager Help
Login

Dark Mode

Channel System-on-Chip (Greenchips-EDU course)

RSS Feeds
Cover Image
13:03
8 - IO Ring Design

IO cell types and ring design

Marcelino Santos

14.11.2025 17:47

Views

55

Cover Image
3:12
7 - Floorplanning SoC

Layout planning, noisy and sensitive signals...

Marcelino Santos

14.11.2025 17:45

Views

39

Cover Image
4:26
6- Digital Backend

Digital P&R with innovus

Marcelino Santos

13.11.2025 17:28

Views

56

Cover Image
4:05
5 - Frontend Views

Datasheet, LEF, verilog model, testbench, liberty...

Marcelino Santos

13.11.2025 17:26

Views

47

Cover Image
16:56
4 - Testability and...

Analog and digital testability

Marcelino Santos

12.11.2025 17:56

Views

78

Cover Image
10:40
3 - Analog and...

Digital Verilog modeling of analog blocks

Marcelino Santos

10.11.2025 18:27

Views

57

Cover Image
12:15
2- Verilog Desigh and...

Verilog for digital design and simulation...

Marcelino Santos

10.11.2025 18:25

Views

69

Cover Image
4:37
1 - SoC Design Flow

From IP to System-on-Chip

Marcelino Santos

10.11.2025 18:18

Views

73